The present invention relates in general to signal processing for computer graphics.
Digital image processing is typically regarded as the most popular method used in display systems. However, one perceived drawback of digital signal processing is the use of high bit counts when digital signals are transmitted between different systems. In addition, a great deal of bandwidth and processing power are required for data transfer. Therefore, the use of analog signals is oftentimes regarded as the prime solution in the application of data transmission between different system interfaces. For example, eight data lines are required for the transmission of an 8-bit digital pixel signal of 256 colors, while one data line provided for the transmission of analog signal is sufficient. Thus, an analog video signal is received by the digital display. The digital display usually samples the analog video signal using a predetermined clock to generate discrete samples. The discrete samples can be used to determine pixel values which may be used to display images on the digital display.
FIG. 1 shows a conventional computer display system. Standard video interface between the PC part 10 and the display part 12 comprises three video signals R/G/B as well as horizontal synchronization signal HSYNC and vertical synchronization signal VSYNC. In the PC part 10, digital pixel data is generated by a graphics circuit 102 and converted by the digital-to-analog converter (DAC) 104 into the associated analog video signals. The analog video signals R/G/B are transmitted, through a cable 14, to the analog-to-digital converter (ADC) 122 of display part 12, which could be a digital display device. The ADC 122 receives the analog video signals and converts them into corresponding digital video signals for image display according to the sampling clock provided by timing generator 124. In other words, the ADC 122 is used to generate the digital video samples corresponding to the digital video data in PC part 10. Then the digital video samples are transmitted to video processing block 126 for further video processing. The quality of the image to be displayed on the display part 12 heavily relies upon whether the analog video signals are sampled by a sampling clock with a correct phase.
FIG. 2 shows amplitude versus time response of a single pixel of an analog video signal for the digital display 12. FIG. 2 also shows two groups 20A and 20B of the sampling points generated by sampling the analog video signal respectively using two sampling clocks with the same sampling period 22 but different phases.
Here, accurate samples are obtained at the sampling points denoted by the arrows in group 20A, since the analog video signal is transient at the sampling points denoted by the dotted arrows in group 20B. Thus, it is important to obtain an accurate sampling timing.
Recently, there were several patents declared to control ADC sampling phase. U.S. Pat. No. 6,268,848 to Eglit discloses a method and apparatus implemented in an automatic sampling phase control system for digital monitors which adjusts the phase of an analog video signal sampling system clock depending upon numerical characteristics of the values of digital samples.
Eglit discloses a method for sampling a plurality of lines of the analog video signal at points in time determined by the delayed sampling clock, detecting peaks and valleys of a signal representing the digital signal digital samples, generating a numerical value based upon relative values of magnitudes of the peaks and valleys, and adjusting the delay of the sampling clock to maximize the numerical value. The numerical value based upon relative values of magnitudes of the peaks and valleys in Eglit is generated by summing the relative value of the magnitudes of the peaks and valleys of the analog video signal.
FIG. 3 shows an example of the relationship between the numerical values and the corresponding sampling phases. Assuming a sampling clock period is divided into 32 phase differences, the digital video signal is sampled using 32 sampling clocks with the phase difference therebetween, and 32 numerical values are generated, with each corresponding to a different sampling phase. In FIG. 3, the abscissa represents the number of the sampling clocks, for example, 1 represents a first sampling clock, and 2 represents a second sampling clock delayed by one phase difference from the first sampling clock. In addition, the ordinate represents numerical values corresponding the sampling clocks in FIG. 2.
The method disclosed in Eglit adjusts the delay of the sampling clock to maximize the numerical value, and uses the adjusted sampling clock as an optimum sampling clock. In FIG. 3, the maximum numerical value is obtained by sampling the analog video signal using the 10th sampling clock. However, the numerical values corresponding to the 9th and the 11th sampling clocks are abruptly decreased. Thus, the maximum numerical value is possibly caused by noise or error detection. This is because in ordinary cases the difference among the accumulation values should not change a lot while there is only slight phase difference among the 9th, the 10th and the 11th sampling clocks. Therefore, the accuracy of the sampled result may deteriorate when the sampling clock corresponding to the maximum numerical value in Eglit is used.